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MX27C1100/27C1024
1M-BIT [128K x 8/64K x 16] CMOS EPROM
FEATURES
* 64K x 16 organization(MX27C1024, JEDEC pin out) * 128K x 8 or 64K x 16 organization(MX27C1100, ROM * * * *
pin out compatible) +12.5V programming voltage Fast access time: 55/70/85/100/120/150 ns Totally static operation Completely TTL compatible
* Operating current: 40mA * Standby current: 100uA * Package type:
- 40 pin plastic DIP - 40 pin plastic SOP - 44 pin PLCC
GENERAL DESCRIPTION
The MX27C1024 is a 5V only, 1M-bit, One Time Programmable Read Only Memory. It is organized as 64K words by 16 bits per word(MX27C1024), 128K x 8 or 64K x 16(MX27C1100), operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM programmers may be used. The MX27C1100/ 1024 supports a intelligent fast programming algorithm which can result in programming time of less than thirty seconds. This EPROM is packaged in industry standard 40 pin dual-in-line packages, 40 lead SOP and 44 lead PLCC packages.
PIN CONFIGURATIONS
PDIP/SOP(MX27C1100)
NC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 NC BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
BLOCK DIAGRAM (MX27C1100)
CE OE BYTE/VPP CONTROL LOGIC OUTPUT BUFFERS Q0~Q14 Q15/A-1
A0~A15 ADDRESS INPUTS
. . . . . . . .
Y-DECODER
X-DECODER
. . . . . . . .
Y-SELECT
MX27C1100
1M BIT CELL MAXTRIX
VCC GND
P/N: PM0156
REV. 4.6, JAN. 14, 2003
1
MX27C1100/27C1024
PIN CONFIGURATIONS
PDIP/SOP(MX27C1024)
VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PGM NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
PLCC(MX27C1024)
PGM VCC VPP Q13 Q14 Q15
A15
Q12 Q11 Q10 Q9 Q8 GND NC Q7 Q6 Q5 Q4
7
6
1 44
A14
40 39 A13 A12 A11 A10 A9 34 GND NC A8 A7 A6 29 28 A5
NC
MX27C1024
12
MX27C1024
17 18
23
Q3
Q2
Q1
Q0
OE
NC
A0
A1
A2
NC
CE
A3
BLOCK DIAGRAM (MX27C1024)
CE PGM OE
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q15
. . A0~A15 ADDRESS INPUTS . . . . . . VCC GND
Y-DECODER
. . . . . . . .
Y-DECODER
X-DECODER
1M BIT CELL MAXTRIX
VPP
A4
P/N: PM0156
2
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
PIN DESCRIPTION(MX27C1100)
SYMBOL A0~A15 Q0~Q14 CE OE BYTE/VPP PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Selection /Program Supply Voltage Q15/A-1 VCC GND Q15(Word mode)/LSB addr. (Byte mode) Power Supply Pin (+5V) Ground Pin
PIN DESCRIPTION(MX27C1024)
SYMBOL A0~A15 Q0~Q15 CE OE PGM VPP VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Enable Input Program Supply Voltage Power Supply Pin (+5V) Ground Pin
TRUTH TABLE OF BYTE FUNCTION(MX27C1100)
BYTE MODE(BYTE = GND)
CE H L L OE X H L Q15/A-1 X X A-1 input MODE Non selected Non selected Selected Q0-Q7 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
WORD MODE(BYTE = VCC)
CE H L L NOTE : X = H or L OE X H L Q15/A-1 High Z High Z DOUT MODE Non selected Non selected Selected Q0-Q14 High Z High Z DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
P/N: PM0156
3
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C1100/1024 When the MX27C1100/1024 is delivered, or it is erased, the chip has all 1M bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C1100/1024 through the procedure of programming. For programming, the data to be programmed is applied with 16 bits in parallel to the data pins. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the MX27C1100/1024. To activate this mode, the programming equipment must force 12.0 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C1100/1024, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q15) defined as the parity bit. VIL(for MX27C1024), OE at VIL, CE at VIH(for MX27C1100)and VPP at its programming voltage.
FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the PGM input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V 10%.
READ MODE The MX27C1100/1024 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - t OE.
PROGRAM INHIBIT MODE Programming of multiple MX27C1100/1024's in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C1100/1024 may be common. A TTL low-level program pulse applied to an MX27C1100/1024 CE input with VPP = 12.5 0.5 V will program the MX27C1100/1024. A high-level CE input inhibits the other MX27C1100/1024s from being programmed.
WORD-WIDE MODE PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE and CE at With BYTE/VPP at VCC 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled.
P/N: PM0156
4
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
BYTE-WIDE MODE With BYTE/VPP at GND 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7. arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
STANDBY MODE The MX27C1100/1024 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC 0.3 V. The MX27C1100/1024 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM
P/N: PM0156
5
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
MODE SELECT TABLE (MX27C1024)
PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIL VIH VCC0.3V VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL X VIL VIL PGM X X X X VIL VIH X X X A0 X X X X X X X VIL VIH A9 X X X X X X X VH VH VPP VCC VCC VCC VCC VPP VPP VPP VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z 00C2H 0115H
NOTES:1. VH = 12.0 V 0.5 V 2 . X = Either VIH or VIL
3. A1 - A8 = A10 - A15 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming.
MODE SELECT TABLE (MX27C1100)
BYTE/ MODE Read (Word) Read (Upper Byte) Read (Lower Byte) Output Disable Standby Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) CE VIL VIL VIL VIL VIH VIL VIH VIH VIL VIL OE VIL VIL VIL VIH X VIH VIL VIH VIL VIL A9 X X X X X X X X VH VH A0 X X X X X X X X VIL VIH Q15/A-1 Q15 Out VIH VIL High Z High Z Q15 In Q15 Out High Z 0B 0B VPP(5) VCC GND GND X X VPP VPP VPP VCC VCC Q8-14 Q8-14 Out High Z High Z High Z High Z Q8-14 In Q8-14 Out High Z 00H 01H Q0-7 Q0-7 Out Q8-15 Out Q0-7 Out High Z High Z Q0-7 In Q0-7 Out High Z C2H 12H
NOTES: 1. VH = 12.0V 0.5V 2. X = Either VIH or VIL 3. A1 - A8, A10 - A15 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltages. 5. BYTE/VPP is intended for operation under DC Voltage conditions only.
P/N: PM0156
6
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
FIGURE 1. FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V VPP = 12.75V X=0
PROGRAM ONE 50us PULSE
INTERACTIVE SECTION
INCREMENT X
YES X = 25?
NO
FAIL
VERIFY WORD
?
PASS NO INCREMENT ADDRESS LAST ADDRESS FAIL YES
VCC = VPP = 5.25V
VERIFY SECTION
VERIFY ALL WORDS ?
FAIL
DEVICE FAILED
PASS DEVICE PASSED
P/N: PM0156
7
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K ohm +5V
CL 6.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF including jig capacitance (30pF for 55/70ns parts)
SWITCHING TEST WAVEFORMS
2.0V
AC driving levels
2.0V TEST POINTS 0.8V OUTPUT
0.8V INPUT
AC TESTING: AC driving levels are 2.4V/0.4V . Input pulse rise and fall times are <20ns.
AC driving levels
1.5V
TEST POINTS OUTPUT
1.5V
INPUT
AC TESTING: (1) AC driving levels are 3.0V/0V. Input pulse rise and fall times are < 10ns. (2) For MX27C1100/1024-55/70
P/N: PM0156
8
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & Vpp VALUE -40oC to 85oC -65oC to 125oC -0.5V to 7.0V -0.5V to VCC + 0.5V -0.5V to 7.0V -0.5V to 13.5V
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
DC/AC Operating Conditions for Read Operation
MX27C1100/1024 -55* Operating Temperature Commercial Industrial ** Vcc Power Supply Vcc 5% 0 to 55C C -70 0C to 70C -85 0 to 70C C -10 0C to 70C -12 0C to 70C -15 0 to 70C C
-40 to 85C -40C to 85C -40 to 85C -40 to 85 -40C to 85C C C C C Vcc 10% Vcc 10% Vcc 10% Vcc 10% Vcc 10%
* : 55ns for MX27C1024 only **:Industrial grade for MX27C1024 only
DC CHARACTERISTICS
SYMBOL VOH VOL VIH VIL ILI ILO ICC3 ICC2 ICC1 IPP PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Power-Down Current VCC Standby Current VCC Active Current VPP Supply Current Read 2.0 -0.3 -10 -10 MIN. 2.4 0.4 VCC + 0.5 0.8 10 10 100 1.5 40 10 MAX. UNIT V V V V uA uA uA mA mA uA VIN = 0 to 5.5V VOUT = 0 to 5.5V CE = VCC 0.3V CE = VIH CE = VIL, f=5MHz, Iout = 0mA CE = OE = VIL, VPP = 5.5V CONDITIONS IOH = -0.4mA IOL = 2.1mA
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL CIN COUT CVPP PARAMETER Input Capacitance Output Capacitance VPP Capacitance TYP. 8 8 18 MAX. 12 12 25 UNIT pF pF pF CONDITIONS VIN = 0V VOUT = 0V VPP = 0V
P/N: PM0156
9
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
AC CHARACTERISTICS
27C1024-55 SYMBOL tACC tCE tOE tDF PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, or CE High to Output Float tOH Output Hold from Address, CE or OE which ever occurred first *tBHA *tOHB *tBHZ *tBLZ BYTE Access Time BYTE Output Hold Time BYTE Output Delay Time BYTE Output Set Time 10 0 70 10 70 0 70 85 ns ns ns ns 0 0 0 ns 0 MIN. MAX. 55 55 30 20 0 27C1100/1024-70 MIN. MAX. 70 70 35 20 0 27C1100/1024-85 MIN. MAX. 85 85 40 25 UNIT ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL
* : for MX27C1100 only
AC CHARACTERISTICS
27C1100/1024-10 SYMBOL tACC tCE tOE tDF PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, or CE High to Output Float tOH Output Hold from Address, CE or OE which ever occurred first *tBHA *tOHB *tBHZ *tBLZ BYTE Access Time BYTE Output Hold Time BYTE Output Delay Time BYTE Output Set Time 10 0 70 10 100 0 70 10 120 0 70 150 ns ns ns ns 0 0 0 ns 0 MIN. MAX. 100 100 45 30 0 27C1100/1024-12 MIN. MAX. 120 120 50 35 0 27C1100/1024-15 MIN. MAX. 150 150 65 50 UNIT ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL
* : for MX27C1100 only
P/N: PM0156
10
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
DC PROGRAMMING CHARACTERISTICS TA = 25oC 5oC
SYMBOL VOH VOL VIH VIL ILI VH ICC3 IPP2 VCC1 VPP1 PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current A9 Auto Select Voltage VCC Supply Current (Program & Verify) VPP Supply Current(Program) Fast Programming Supply Voltage Fast Programming Voltage 6.00 12.5 2.0 -0.3 -10 11.5 MIN. 2.4 0.4 VCC + 0.5 0.8 10 12.5 50 30 6.50 13.0 MAX. UNIT V V V V uA V mA mA V V CE = VIL, OE = VIH VIN = 0 to 5.5V CONDITIONS IOH = -0.40mA IOL = 2.1mA
AC PROGRAMMING CHARACTERISTICS TA = 25oC 5C
SYMBOL tAS tOES tDS tAH tDH tDFP tVPS tPW tVCS tCES tOE PARAMETER Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay VPP Setup Time PGM Program Pulse Width VCC Setup Time CE Setup Time Data valid from OE MIN. 2.0 2.0 2.0 0 2.0 0 2.0 95 2.0 2.0 150 105 130 MAX. UNIT us us us us us ns us us us us ns CONDITIONS
P/N: PM0156
11
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
WAVEFORMS(MX27C1024)
READ CYCLE(WORD MODE)
ADDRESS INPUTS
tACC
DATA ADDRESS
CE
tCE
OE
tDF
DATA OUT
tOE
VALID DATA
tOH
FAST PROGRAMMING ALGORITHM WAVEFORMS
PROGRAM VIH
PROGRAM VERIFY
Addresses
VIL
tAS
Hi-z DATA IN STABLE DATA OUT VALID
tAH
DATA
tDS VPP1
tDH
tDFP
VPP
VCC tVPS VCC1
VCC
VCC VIH
tVCS
CE
VIL tCES VIH
PGM
VIL tPW VIH tOES tOE Max
OE
VIL
P/N: PM0156
12
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
WAVEFORMS(MX27C1100)
READ CYCLE(BYTE MODE)
A-1
HIGH-Z
HIGH-Z
tACC
tOH
BYTE/VPP
Q0-Q7
VALID DATA
tBHA tOHB
VALID DATA
Q15-Q8
tBHZ tBLZ
VALID DATA
FAST PROGRAMMING ALGORITHM WAVEFORM
PROGRAM VIH VERIFY
Addresses
VIL
VALID ADDRESS
tAH tAS
DATA
tDS VPP1
DATA SET
tDH
DATA OUT VALID
tDFP
BYTE/VPP
VCC tVPS VCC1
VCC
VCC VIH
tVCS
CE
VIL tPW VIH tOES tOE
OE
VIL
P/N: PM0156
13
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
ORDER INFORMATION PLASTIC PACKAGE
PART NO. MX27C1100PC-70 MX27C1100PC-85 MX27C1100PC-10 MX27C1100PC-12 MX27C1100PC-15 MX27C1100MC-70 MX27C1100MC-85 MX27C1100MC-10 MX27C1100MC-12 MX27C1100MC-15 MX27C1024PC-55 MX27C1024PC-70 MX27C1024PC-85 MX27C1024PC-10 MX27C1024PC-12 MX27C1024PC-15 MX27C1024QC-55 MX27C1024QC-70 MX27C1024QC-85 MX27C1024QC-10 MX27C1024QC-12 MX27C1024QC-15 MX27C1024MC-55 MX27C1024MC-70 MX27C1024MC-85 MX27C1024MC-10 MX27C1024MC-12 MX27C1024MC-15 ACCESS TIME (ns) 70 85 100 120 150 70 85 100 120 150 55 70 85 100 120 150 55 70 85 100 120 150 55 70 85 100 120 150 OPERATING CURRENT MAX.(mA) 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 STANDBY CURRENT MAX.(uA) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 40 Pin DIP(ROM pin out) 40 Pin DIP(ROM pin out) 40 Pin DIP(ROM pin out) 40 Pin DIP(ROM pin out) 40 Pin DIP(ROM pin out) 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin DIP(JEDEC pin out) 40 Pin DIP(JEDEC pin out) 40 Pin DIP(JEDEC pin out) 40 Pin DIP(JEDEC pin out) 40 Pin DIP(JEDEC pin out) 40 Pin DIP(JEDEC pin out) 44 Pin PLCC 44 Pin PLCC 44 Pin PLCC 44 Pin PLCC 44 Pin PLCC 44 Pin PLCC 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin SOP 40 Pin SOP PACKAGE
P/N: PM0156
14
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
PACKAGE INFORMATION
P/N: PM0156
15
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
P/N: PM0156
16
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
P/N: PM0156
17
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
REVISION HISTORY
Revision No. Description 3.0 Revise speed grade from 70/90/120/150ns to 55/70/85/100/ 120/150ns. Add 40 pin SOP package type. 4.0 1) Eliminate Interactive Programming Mode. 2) 40-CDIP package quartz lens, change to square shape. 4.1 IPP : 100uA ----> 10uA 4.2 Add industrial grade 70/85/100/120/150ns 40-TSOP(I) 4.3 Cancel ceramic DIP package type 4.4 Cancel "Ultraviolet Erasable" wording in General Description To modify Package Information 4.5 To modify Package Information 4.6 1. To remove 10 x 14mm 40-TSOP package type. 2. To modify 40-PDIP package information Page Date 10/15/1996
06/14/1997 08/08/1997 11/19/1998 FEB/25/2000 AUG/20/2001 NOV/19/2002 JAN/14/2003
P15 P1,2,4,15,16 P1 P15~18 P15~18 P1,2,14,18 P15
P/N: PM0156
18
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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